ENEE 611 (696): Integrated and Microwave Electronics

Course Goals:

This course covers the design of analog integrated circuits, both bipolar and MOS.

Course Prerequisite:

The course is self-contained, but some previous experience in circuit design is helpful.

Present Texts:

P.R. Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuits.
A.B. Grebene, Bipolar and MOS Analog Integrated Circuit Design.

Core Topics:

  • Integrated-Circuit Fabrication and Device Models: Basic processing steps; npn and pnp devices; enhancement and depletion mos devices; diodes, resistors and capacitors; large and small signal models; calculating device parasitics; I-V characteristics.
  • Bias Circuits: Current source design; output resistance; output voltage source design; DC level-shift design; supply voltage sensitivity; temperature coefficient; temperature-independent biasing.
  • Gain Stages: Finding input resistance, output resistance, gain, and transconductance for various transistor configurations; emitter-coupled and source-coupled pairs; large signal characteristic; gain stages with active loads; common-mode gain; differential-mode gain; CMRR; differential input resistance; common mode input resistance; input offset voltage; input offset current; offset drift; output stages.
  • Operational Amplifiers: Op amp circuits; real op amps: input offset voltage, input bias current, input offset current, input resistance, output resistance, input common-mode range, common-mode rejection ratio, power supply rejection ration, open-loop voltage gain, unity-gain bandwidth, slew rate, full-power bandwidth, settling time; op amp stability: Nyquist criteria, gain margin, phase margin; op amp analysis: dc analysis, ac analysis, input offset voltage.
  • Wideband Amplifiers: Frequency response; common-emitter stage, emitter follower stage, common-base stage, multiple stages, zero-value time constant analysis; feedback: series-shunt, shunt-shunt shunt-series, series-series, local feedback, feedback, cascades, overall feedback; root-locus techniques; compensation methods, narrowbanding, pole splitting, feedback zero.

Comments:

Students in sections of this course can fabricate VLSI chips via MOSIS.