ENEE 644: Computer-Aided Design of Digital Systems

UMCP ENEE 644 Indepth Course Description

Course Goals:

Present a new design methodology for digital systems using a modern hardware description language (HDL). Learn algorithm, architecture, and implementation aspects of arithmetic processing elements such as adders, multipliers, and dividers. Study architecture designs of CISC, RISC, and floating-point arithmetic processors. Emphasize parallelism and pipelining techniques in digital system design.

With the use of a simulation/synthesis environment of the HDL as well as other CAD tools such as a layout tool and a tester, evaluate, implement as hardware, and test such digital systems. Also study basic techniques and methodologies used in such CAD tools. Emphasize the concept of design for testability.

Course Prerequisite:

ENEE 446 or equivalent; and ENEE 449 or equivalent.

Topic Prerequisite:

Basic knowledge of digital logic design (switching functions, combinational and sequential circuits, register transfers, ROMs, RAMs), and computer architecture (instruction set architecture, addressing, interrupts, branching, data path). Basic understanding of arithmetic and matrix operations.

Reference Books:

  1. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann.
  2. I. Koren, Computer Arithmetic Algorithms, Prentice Hall, 1993.
  3. K. Hwang and F. A. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill, 1984.
  4. M. D. Ercegovac and T. Lang, Digital Systems and Hardware/Firmware Algorithms, John Wiley & Sons, 1985.
  5. D. P. Siewiorek, C. G. Bell, and A. Newell, Computer Structures: Principles and Examples, McGraw Hill, 1982.
  6. Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, 1978.
  7. H. Fujiwara, Logic Testing and Design for Testability, MIT Press, 1985.
  8. D. L. Parry, VHDL, 2nd Ed., McGraw Hill, 1994.
  9. G. De Micheli, Synthesis and Optimization of digital Circuits, McGrraw-Hill, 1994.
  10. Z. Navabi, VHDL: Analysis and Modeling of Digital Systems, McGraw-Hill, 1993.
  11. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1990.

Reference Papers:

  1. Y. Nakamura, K. Oguri, and A. Nagoya, "Synthesis From Pure Behavioral Descriptions," in High-Level VLSI Synthesis, R. Camposano and W. Wolf, Eds., Kluwer Academic Publishers, 1991, pp. 205-229.
  2. Y. Nakamura, "An Integrated Logic Design Environment Based on Behavioral Description," IEEE Trans. on Computer-Aided Design, Vol. CAD-6, No. 3, pp. 322-336, 1987.
  3. R. K. Brayton, G. D. Hachtel, A. L. Sangiovanni-Vincentelli, "Multilevel Logic Synthesis," Proceedings of the IEEE, Vol. 78, No. 2, pp. 264 - 300, Feb. 1990.
  4. M. C. McFarland, A. C. Parker, and R. Camposano, "The High-Level Synthesis of Digital Systems," Proceedings of the IEEE, Vol. 78, No. 2, pp. 301--318, Feb. 1990.
  5. T. W. Williams and K. P. Parker, "Design for Testability -- A Survey," Proceedings of the IEEE, Vol. 71, No. 1, pp. 98--112, Jan. 1983.

Core Topics:

  • Design Description and Abstraction: graphical representation versus description by language, design hierarchy of digital systems.
  • Review of Logic Design and Computer Architecture: combinational circuits, sequential circuits, simple machine architecture.
  • Hardware Description Language: basic features of the language, sample HDL-based designs (e.g., 7-segment display, finite state machine, up/down counter, hand-held calculator).
  • Arithmetic Processing Element Design: adders, multipliers, dividers.
  • Processor Design: CISC processors, RISC processors, floating-point arithmetic processors
  • Techniques for CAD Tool Development: logic simulation, logic minimization, logic testing, design for testability, system partitioning, physical layout.

Optional Topics:

  • Sorting Networks.
  • Systolic Arrays.
  • Matrix Computations.
  • Digital Signal Processors.

Comments:

The HDLs to be used may include the IEEE standard VHDL and the SFL (Structured Function description Language)of a high-level hardware synthesis system, called PARTHENON.

Last Updated:

September 1995.