Rajeev  Barua
Assistant Professor
HTML-Resume
   Rajeev K. Barua
1431 A. V. Williams Building
Department of Electrical and Computer Engineering
University of Maryland 
College Park, MD 20742
Office: (301)-405-8137
Fax: (301)-314-9281
barua@eng.umd.edu
http://www.ece.umd.edu/~barua/
RESEARCH INTERESTS
 
 
 
 

Jan 2000 - present

May 2000-present
 

 Compilers and Computer Architecture. I am particularly interested in designing new architecture-aware compiler techniques for general-purpose microprocessors and embedded designs.

University of Maryland                                           College Park, MD
Assistant Professor, Department of Electrical and Computer Engineering. 
Affiliate Professor, Department of Computer Science.
 
EDUCATION Massachusetts Institute of Technology                 Cambridge, MA
Ph.D in Computer Science and Electrical Engineering   January, 2000.   Thesis:   "Maps: A Compiler-Managed Memory System for Software-Exposed Architectures" 
Advisors:   Anant Agarwal and Saman Amarasinghe 
Graduate GPA:    4.9/5.0 

Massachusetts Institute of Technology                 Cambridge, MA
M.S in Computer Science and Electrical Engineering             May, 1994 
Thesis:   "Global partitioning of Parallel Loops and Data Arrays  for Caches and  Distributed Memory in  Multiprocessors" 
Advisor:  Anant Agarwal 

Indian Institute of Technology                                New Delhi, India 
B.Tech in Computer Science                                                  May 1992 
GPA:   9.86/10.00  Graduated as first in the department and institute
DISSERTATION  Thesis:   "Maps: A Compiler-Managed Memory System for Software-Exposed Architectures" 
Advisors:  Anant Agarwal and Saman Amarasinghe 
 My thesis presents Maps , a compiler system for handling memory efficiently on software-exposed architectures. A software-exposed architecture is one in which the low level details of the hardware,  such as functional units and memory banks, are visible to the software. There is a growing interest in such architectures not only for general-purpose computation, but for multimedia and embedded  computation as well. These architectures are able to orchestrate a high degree of ILP and memory parallelism in the compiler.  The thesis presents a solution to the difficult problem of how to distribute data in sequential programs among several banks to best exploit memory parallelism, and yet retain the ability to disambiguate references to particular banks. It enables both a high degree of memory parallelism, and on Raw the use of a fast compiler-routed static network rather than a slower dynamic network. Static memory disambiguation may also be useful in other architectures that exploit ILP and have multiple banks with non-uniform access times. Maps also shows how to efficiently orchestrate non-disambiguated accesses in addition to disambiguated accesses. Results on Raw using sequential codes demonstrate roughly 20-fold speedup on 32 tiles for our regular applications and about 5-fold speedup on 16 or more tiles for our irregular applications. 
RESEARCH EXPERIENCE
Jan 2000-present 
 
 

1996-Jan 2000
Assistant Professor           University of Maryland, College Park
Department of Electrical and Computer Engineering.  Research
program in innovative compiler techniques for highly exposed
general-purpose and multimedia processors.
Member, Raw group         Massachusetts Institute of Technology 
Founding member of the Raw group, and one of two principal architects of the Raw compiler, RAWCC. Actively involved in the initial architectural design decisions. Designed the first assembly level instruction set specification for the Raw prototype.  First proposed the global control flow model called asynchronous global branching for the Raw compiler, and co-discovered control localization with Walter Lee. Developed modulo unrolling method for memory disambiguation for regular programs.  Co-discovered equivalence-class unification with Walter Lee.  Implemented these and other Maps techniques using SUIF as part of RAWCC compiler. Maintained extensive Maps infrastruture now used by several group members. Maps system now also used as one of the underpinnings of the Smart Memories project at MIT.
 1995 Quantifying Communication Mechanisms     Massachusetts Institute of Technology 
Compared multiprocessor mechanisms including shared memory with and without prefetching,  message passing with interrupts and with polling, and bulk transfer via DMA. Ported several applications using these different styles onto MIT Alewife machine. Varied bisection bandwidth and  network latency to measure impact. 
1992-1994 Multiprocessor Compilation   Massachusetts Institute of Technology 
Designed scheme for automatic data and loop partitioning for regular programs written using explicitly parallel doall constructs.  The scheme  minimized communication while maintaining load balance. Results were  demonstrated on the MIT Alewife machine. Also designed an all-software method for efficient addressing of distributed data termed Software Virtual Memory. This method  has resurfaced in the Raw project as well.
TEACHING EXPERIENCE
Spring 2000
 

Spring,1995
University of Maryland, College Park
Led course ENEE759C, "Compiler Optimizations for Modern Architectures". 
Teaching Assistant            Massachusetts Institute of Technology 
For graduate-level computer architecture course taught by Prof. Arvind. Duties included teaching weekly recitation sections to a group of 30-40   students. Also prepared new problem sets and examinations. Helped with grading
 1990 Voluntary tutoring as community service              New Delhi, India
Tutored poor school children from a village near my undergraduate institution. 
PREVIOUS WORK EXPERIENCE 
 Summer 1993		 Motorola Cambridge Research Center               Cambridge, MA
Designed loop and data partitioning scheme for distributed memory machines without global caches, such as START. Evaluated various compiler and hardware features on START using simulations, and suggested improvements. 
 Summer 1991 Central Railway Information Systems                 New Delhi, India
Developed a natural language parser, and an automatic parser generator for computer translation of English to Hindi
 Summer 1990 Indian Institute of Technology                             New Delhi, India 
Developed a router for visual display of digital circuits at IIT Delhi's CAD  laboratory. 
AWARDS 
  • President of India Gold Medal, 1992 (For 1/300 rank, B.Tech class of '92). 
  • Motorola Award for Undergraduate Research : "A simulator and performance evaluator  for different dataflow architectures", 1991.
  • Recipient, Government of India Merit Scholarship, 1990-1992. 
  • National Champion, Rotary Club debating competition, 1988
   
   
Refereed Publications:  Other Publications: 

  Ph.D Thesis: