Bruce Jacob University of Maryland Memory-Systems Research Keystone Professor and Director of Computer Engineering Department of Electrical & Computer Engineering University of Maryland at College Park College Park, MD 20742 E-mail: blj@ece.umd.edu WWW: http://www.ece.umd.edu/~blj/ Photo: Axel Persaud (a former student and photographer-on-the-side)

Office: 1325 A.V. Williams
Phone: +1 301-405-0432
Fax: +1 301-314-9281

Brief NSF/IEEE-style bio (for when you need such things)

Education

• A.B. (Mathematics, cum laude) Harvard University - Cambridge MA, 1988
• M.S. (Computer Science & Engineering) University of Michigan - Ann Arbor MI, 1995
• Ph.D. (Computer Science & Engineering) University of Michigan - Ann Arbor MI, 1997

Industry Experience

• Software Engineer, Boston Technology - Cambridge MA + Wakefield MA, 1989-1991
  (now part of Comverse Network Systems [who seem to have changed their name to Comverse Technology])
• Chief Engineer & System Architect, Priority Call Management - Wilmington MA, 1991-1992
  (now part of LHS Group [which is actually now part of Sema Group {which seems to be part of Schlumberger at this point ... I'm losing track}])
  (and, as of 2004, they're part of uReach Technologies ... I think I will give up on keeping this up-to-date)

Computational Artifacts

• DRAMsim, our public-domain DRAM-system simulator, at http://www.ece.umd.edu/dramsim
• BioBench, our set of bioinformatics workloads, at http://www.ece.umd.edu/biobench

Honors & Awards

• Clark School of Engineering Keystone Professor, 2006
• University of Maryland "Rainmaker," 2005
• IBM Shared University Research Award, 2005
• University of Maryland Award for Teaching Excellence, 2004
• Tenure Awarded, 2003
• University of Maryland "Rainmaker," 2001
• National Science Foundation CAREER Award, 2000
• ECE Department George Corcoran Award, 1999

Research Interests

• Memory systems (DRAM systems, virtual memory, cache design, etc.)
  
• Embedded systems (SimBed, low-power issues, real-time caches, hardware support for RTOSes, etc.)
• Circuit integrity (EMI issues and EMI-tolerant architectures, RF measurements, thermal issues, etc.)
• Computer architecture & microarchitecture
• Low-level operating systems design
• Verilog modeling (e.g. 16-bit out-of-order RiSC-16)
• Algorithmic composition (e.g. some composition software and MP3's of a 35-minute orchestral piece)

University of Maryland Memory-Systems Research

• Overview & FAQ
• Computational artifacts
• Workloads and their characterization
• The many, many studies

Research Group: Grad Students, 2003 Grad Students, 2006

Selected Publications

2007	Open letter	"On supporting a high-tech cottage industry ... an open letter to the engineering-education community." (in particular, the computer-design subset of engineering, but, hey, everyone is invited) Bruce Jacob. December 2007.
	Morgan Kaufmann book	Memory Systems: Cache, DRAM, Disk. Bruce Jacob, Spencer Ng, and David Wang, with contributions by Samuel Rodriguez. ISBN 978-0-12-379751-3. Morgan Kaufmann Publishers, September 2007. Approx. 1000 pages, 500,000 words. As a teaser, here is PDF of the book's Overview chapter, "On Memory Systems and Their Design". Clicking the link above or the image of the cover will take you to the Morgan Kaufmann website, where you can get yourself one of these rare beauties. Alternatively: check it out on Amazon.com. By the way, all the websites have it wrong: it is hardcover, not softcover.
	HPCA	"Fully-Buffered DIMM memory architectures: Understanding mechanisms, overheads and scaling." Brinda Ganesh, Aamer Jaleel, David Wang, and Bruce Jacob. Proc. 13th International Symposium on High Performance Computer Architecture (HPCA 2007), pp. 109-120. Phoenix AZ, February 2007.
2006	CASES	"Modeling heterogeneous SoCs with SystemC: A digital/MEMS case study." A. Varma, Y. Afridi, A. Akturk, P. Klein, A. Hefner, and B. Jacob. Proc. International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES 2006), pp. 54-64. Seoul Korea, October 2006.
	ISLPED	"Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)." Samuel V. Rodriguez and Bruce Jacob. Proc. International Symposium on Low Power Electronics and Design (ISLPED 2006), pp. 25-30. Tegernsee Germany, October 2006.
	HPCA	"Last-level cache (LLC) performance of data-mining workloads on a CMP--A case study of parallel bioinformatics workloads." Aamer Jaleel, Matthew Mattina, and Bruce Jacob. Proc. 12th International Symposium on High Performance Computer Architecture (HPCA 2006), pp. 88-98. Austin TX, February 2006.
	E&M	"Electromagnetic interference and digital circuits: An initial study of clock networks." Hongxia Wang, Samuel V. Rodriguez, Cagdas Dirik, and Bruce Jacob. Electromagnetics, vol. 26, no. 1, pp. 73-86. January 2006. (Special Issue: RF effects on Digital Systems)
	IEEE-TC	"In-line interrupt handling and lock-up free translation lookaside buffers (TLBs)." Aamer Jaleel and Bruce Jacob. IEEE Transactions on Computers, vol. 55, no. 5, pp. 559-574. May 2006.
2005	HPCA	"Using Virtual Load/Store Queues (VLSQs) to reduce the negative effects of reordered memory instructions." Aamer Jaleel and Bruce Jacob. Proc. 11th International Symposium on High Performance Computer Architecture (HPCA 2005), pp. 191-200. San Francisco CA, February 2005.
	ISPASS	"BioBench: A benchmark suite of bioinformatics applications." K. Albayraktaroglu, A. Jaleel, X. Wu, M. Franklin, B. Jacob, C.-W. Tseng, and D. Yeung. Proc. 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2005), pp. 2-9. Austin TX, March 2005.
	SIGARCH	"DRAMsim: A memory-system simulator." David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Katie Baynes, Aamer Jaleel, and Bruce Jacob. SIGARCH Computer Architecture News, vol. 33, no. 4, pp. 100-107. September 2005.
2004	ISCA	"Extended Split-Issue: Enabling flexibility in the hardware implementation of NUAL VLIW DSPs." Bharath Iyer, Sadagopan Srinivasan, and Bruce Jacob. Proc. 31st International Symposium on Computer Architecture (ISCA 2004), pp. 364-375. Munchen Germany, June 2004.
	EMC	"Radio frequency effects on the clock networks of digital circuits." Hongxia Wang, Cagdas Dirik, Samuel V. Rodriguez, Amol V. Gole and Bruce Jacob. Proc. IEEE International Symposium on Electromagnetic Compatibility (EMC 2004), pp. 93-96. Santa Clara CA, August 2004.
	JSSE	"MEMS-based embedded sensor virtual components for system-on-a-chip (SoC)." M. Afridi, A. Hefner, D. Berning, C. Ellenwood, A. Varma, B. Jacob, S. Semancik. Journal of Solid-State Electronics, vol. 48, no. 10/11, pp. 1777-1781. October/November 2004.
2003	CASES	"A control-theoretic approach to dynamic voltage scaling." A. Varma, B. Ganesh, M. Sen, S. R. Choudhary, L. Srinivasan, and B. Jacob. Proc. International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES 2003), pp. 255-266. San Jose CA, October 2003.
	CODES+ISSS	"Hardware support for real-time operating systems." Paul Kohout, Brinda Ganesh, and Bruce Jacob. Proc. First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2003), pp. 45-51. Newport Beach CA, October 2003.
	IEEE-TC	"The performance and energy consumption of embedded real-time operating systems." K. Baynes, C. Collins, E. Fiterman, B. Ganesh, P. Kohout, C. Smit, T. Zhang, and B. Jacob. IEEE Transactions on Computers, vol. 52, no. 11, pp. 1454-1469. November 2003.
	IEEE Micro	"A case for studying DRAM issues at the system level." Bruce Jacob. IEEE Micro, vol. 23, no. 4, pp. 44-56. July/August 2003.
2001	ISCA	"Concurrency, latency, or system overhead: Which has the largest impact on uniprocessor DRAM-system performance?" Vinodh Cuppu and Bruce Jacob. Proc. 28th International Symposium on Computer Architecture (ISCA 2001), pp. 62-71. Goteborg Sweden, June 2001.
	CASES	"Transparent data-memory organizations for digital signal processors." Sadagopan Srinivasan, Vinodh Cuppu, and Bruce Jacob. Proc. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2001), pp. 44-48. Atlanta GA, November 2001.
	CASES	"The performance and energy consumption of three embedded real-time operating systems." K. Baynes, C. Collins, E. Fiterman, B. Ganesh, P. Kohout, C. Smit, T. Zhang, and B. Jacob. Proc. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2001), pp. 203-210. Atlanta GA, November 2001.
	IEEE-TC	"High performance DRAMs in workstation environments." Vinodh Cuppu, Bruce Jacob, Brian Davis, and Trevor Mudge. IEEE Transactions on Computers, vol. 50, no. 11, pp. 1133-1153. November 2001. (TC Special Issue on High-Performance Memory Systems)
	IEEE-TC	"Uniprocessor virtual memory without TLBs." Bruce Jacob and Trevor Mudge. IEEE Transactions on Computers, vol. 50, no. 5, pp. 482-499. May 2001.
1999	ISCA	"A performance comparison of contemporary DRAM architectures." Vinodh Cuppu, Bruce Jacob, Brian Davis, and Trevor Mudge. Proc. 26th International Symposium on Computer Architecture (ISCA 1999), pp. 222-233. Atlanta GA, May 1999.
1998	ASPLOS	"A look at several memory management units, TLB-refill mechanisms, and page table organizations." Bruce Jacob and Trevor Mudge. Proc. Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 1998), pp. 295-306. San Jose CA, October 1998.
	IEEE Micro	"Virtual memory in contemporary microprocessors." Bruce Jacob and Trevor Mudge. IEEE Micro, vol. 18, no. 4, pp. 60-75. July/August 1998.
	IEEE Computer	"Virtual memory: Issues of implementation." Bruce Jacob and Trevor Mudge. IEEE Computer, vol. 31, no. 6, pp. 33-43. June 1998.
1997	HPCA	"Software-managed address translation." Bruce Jacob and Trevor Mudge. Proc. Third International Symposium on High Performance Computer Architecture (HPCA'97), pp. 156-167, San Antonio TX, February 1997.
1996	Organised Sound	"Algorithmic composition as a model of creativity." Bruce Jacob. Organised Sound, vol. 1, no. 3, pp. 157-165. Cambridge University Press. December 1996.
	IEEE-TC	"An analytical model for designing memory hierarchies." Bruce Jacob, Peter Chen, Seth Silverman, and Trevor Mudge. IEEE Transactions on Computers, vol. 45, no. 10, pp. 1180-1194. October 1996.
1995	ICMC	"Composing with genetic algorithms." Bruce Jacob. Proc. International Computer Music Conference (ICMC '95), pp. 452-455. Banff Alberta, September 1995.

All Publications

Talks & Presentations

Students: Awards/Honors, Research Topics, and Theses

Student Honors:
Aamer Jaleel	Award for Best Paper Presentation, 11th International Symposium on High Performance Computer Architecture (HPCA 2005), February 2005.
Christine Smit	Chosen to be Student Speaker at University of Maryland Campus-Wide Commencement, May 20th, 2004.
Sandy Klemm	2002 Merit Fair First Place Winner for his undergraduate research on dynamic voltage scaling.
Current Students:
Cagdas Dirik	A complete system-level fault-tolerant approach for electromagnetic interference. Electromagnetic Interference (EMI) can have an adverse effect on commercial electronics. As feature sizes of integrated circuits become smaller, their susceptibility to such EMI increases. In light of this, integrated circuits will face substantial problems in the future either from electromagnetic disturbances or intentionally generated EMI from a malicious source (intentional EMI). In this work we introduce a fault tolerant architecture, TERPS, which can significantly reduce the threat of intentional EMI in computer systems.
Hongxia Wang	Circuit integrity issues and electromagnetic interference. Due to reduced feature sizes, voltage levels, and switching delays, modern digital systems are becoming more susceptible to elecromagnetic emissions (noise), thermal effects, and voltage fluctuations. This work characterizes the EMI sources of circuit integrity issues: in particular, the exact nature of errors.
Ph.D. Theses:
Sadagopan Srinivasan	Ph.D. 2007. Prefetching vs. the Memory System: Optimizations for Multi-core Server Platforms. (Intel) Investigates prefetching scheme for servers with respect to realistic memory systems. Real systems disable prefetching in server settings, suggesting that there is a fundamental disconnect between research and practice. This thesis shows that the disconnect is due to the use of simplistic memory models; experimental results suggest that using simplistic models can mis-predict the system performance by a factor of two.
Brinda Ganesh	Ph.D. 2007. Understanding and Optimizing High-Speed Serial Memory-System Protocols. (Intel) Next-generation memory systems such as the Fully-Buffered DIMM use a system topology more akin to a computer network than a traditional memory bus. Data movement in these systems is complicated by the bus organization, making it essential to understand the implications when designing schedulers for these systems.
Ankush Varma	Ph.D. 2007. High-Speed Performance, Power, and Thermal Co-Simulation for SoC Design. (Intel) Developing tools and methodologies for fast, accurate, high-level power and thermal modeling on SoCs. Exploring power/thermal modeling for MEMS, mixed-signal and digital SoC components, how these models can be built into high-level System Description Languages (such as SystemC), and how high-level power models can be made robust to low-level design decisions.
Nuengwong (Ohm) Tuaycharoen	Ph.D. 2006. Disk Design-Space Exploration in Terms of System-Level Performance, Power, and Energy Consumption. (Dhurakijpundit University) SYSim is a full-system simulator that integrates Bochs, Wattch, DRAMsim, and DiskSim, boots Linux, and enables complete memory hierarchy studies in both performance and power consumption domains. With it, we investigate the system-level impacts of disk- and DRAM-system technologies such as DRAM capacity, disk caching, disk speed, etc.
Samuel Rodriguez	Ph.D. 2006. myCACTI: A New Cache-Design Tool for Pipelined Nanometer Caches. (AMD) This dissertation shows that both CACTI and eCACTI still contain major limitations and even flaws in their design, making them unsuitable for use in very-deep submicron and nanometer caches, especially pipelined designs. These limitations and flaws are discussed in detail. This dissertation then introduces a new tool, called myCACTI, that addresses all these limitations and, in addition, introduces major enhancements to the simulation framework.
Aamer Jaleel	Ph.D. 2005. The Effects of Out-of-Order Execution on the Memory System. (Intel) Studies the deleterious effects of out-of-order execution. Common wisdom holds that bigger is better: to wit, the larger the instruction window, the better the performance. Numerous studies show this result, and, consequently, numerous other studies investigate low-cost ways to implement large instruction windows. This study shows that, once one includes a realistic model of the memory system, nearly all of those projected performance gains fail to materialize.
David Tawei Wang	Ph.D. 2005. Modern DRAM Memory Systems: Performance Analysis and a High Performance, Power-Constrained DRAM-Scheduling Algorithm. (MetaRAM) An in-depth treatment of modern, power-limited, DRAM systems. The timing parameters tFAW and tRRD, introduced at the DDR2 generation of DDRx SDRAM, have a deleterious effect on system-level performance, significantly limiting sustainable bandwidth. The work characterizes the problem and provides a scheduling algorithm that offers a solution. As of February 2008, MetaRAM is now radar-visible. Fred, Dave, and Co. are set to take over the world.
Brian Davis	Ph.D. 2001. Modern DRAM Architectures. (Michigan Tech) This thesis examines a variety of modern DRAM architectures in the context of current desktop workstations. The DRAM examined (EDO, Burst EDO, SDRAM, DDR, DDR2, Rambus, ESDRAM, FCRAM, VCM) include those which are available today, as well as a number of architectures which are expected to come to market in the near future. (co-advised by Trevor Mudge)
M.S. Theses:
Jeffrey Scott Smith	M.S. 2006. Distributed Two-Dimensional Fourier Transforms on DSPs with Applications for Phase Retrieval. (NASA)
Rami Nasr	M.S. 2005. FBsim and the Fully Buffered DIMM Memory System Architecture. (Lutron)
Amol Gole	M.S. 2003. TERPS: The Embedded Reliable Processing System. (General Dynamics Robotics Systems)
Bharath Iyer	M.S. 2003. Extended Split-Issue Mechanism in VLIW DSPs to Support SMT and Hardware-ISA Decoupling. (AMD)
Nuengwong (Ohm) Tuaycharoen	M.S. 2003. RTOS-Based Dynamic Voltage Scaling. (continuing as U. Maryland Ph.D. student)
Lei Zong	M.S. 2003. Nanoprocessors: Configurable Hardware Accelerators for Embedded Systems. (Army Research Lab)
Brinda Ganesh	M.S. 2002. Architectural Support for Embedded Operating Systems. (continuing as U. Maryland Ph.D. student)
Aamer Jaleel	M.S. 2002. In-Line Interrupt Handling and Lockup-Free TLBs. (continuing as U. Maryland Ph.D. student)
Paul Kohout	M.S. 2002. Hardware Support for Real-Time Operating Systems. (EVI Technology)
Tiebing Zhang	M.S. 2001. RTOS Performance and Energy Consumption Analysis Based on an Embedded System Testbed. (Aeptec Microsystems)
Christopher Collins	M.S. 2000. An Evaluation of Embedded System Behavior Using Full-System Software Emulation. (Intel)

Past, Present, and Future Classes

Fall 2008:	ENEE 646, Digital Computer Design ENES 100, Introduction to Engineering Design
Spring 2008:	ENEE 359a, Digital VLSI Circuits ENEE 159b, Electric Guitar Design (Start-Up 101) ENES 100, Introduction to Engineering Design
Fall 2007:	ENEE 759h, High-Speed Memory Systems ENES 100, Introduction to Engineering Design
Spring 2007:	ENEE 359a, Digital VLSI Circuits ENES 100, Introduction to Engineering Design
Fall 2006:	ENEE 646, Digital Computer Design ENES 100, Introduction to Engineering Design
Spring 2006:	ENEE 446, Digital Computer Design
Fall 2005:	ENEE 302H, Digital Electronics
Spring 2005:	HONR 218V, Digital Sound and Fury on Mac OSX: Desktop Publishing, Music, Photography, and Video ENEE 759h, High-Speed Memory Systems
Fall 2004:	ENEE 302H, Digital Electronics
Spring 2004:	On sabbatical
Fall 2003:	On sabbatical
Spring 2003:	ENES 100, Introduction to Engineering Design ENEE 759h, High-Speed Memory Systems
Fall 2002:	ENEE 646, Digital Computer Design
Spring 2002:	ENEE 759m, Advanced Topics in Microarchitecture
Fall 2001:	ENEE 646, Digital Computer Design
Spring 2001:	ENEE 350, Computer Organization
Fall 2000:	ENEE 446, Digital Computer Design
Spring 2000:	ENEE 759m, Advanced Topics in Microarchitecture
Fall 1999:	ENEE 350, Computer Organization
Spring 1999:	ENEE 647, Distributed Computer Systems
Fall 1998:	ENEE 350H, Computer Organization ENEE 698b, Graduate Seminar in Computer Engineering
Spring 1998:	ENEE 759m, Advanced Topics in Microarchitecture
Fall 1997:	ENEE 350H, Computer Organization